This invention relates generally to isolation circuits, and more particularly, it relates to a high voltage isolation circuit for CMOS networks wherein a N-channel MOS pass transistor is used to isolate a high voltage node from a low voltage node so as to prevent CMOS latch-up.
As is well known, a CMOS network consisting of an inverter may be formed of a monolithic integrated circuit containing field-effect transistors (FET) in which regions of one conductivity, such as a P-type, are diffused in a substrate of a complementary conductivity, such as a N-type. A problem exists when different portions of the integrated circuit are operated at two different voltage levels. For example, if the P-conductivity type regions defining source and drain electrodes of the FET were operated at a first higher voltage (i.e, 15 volts) and the N-conductivity forming the substrate was operated at a second lower voltage (i.e., 5 volts), the PN junctions thus formed would be forward biased which can trigger a CMOS latch-up. As a result, excessive high currents may flow to cause burn-out of the junctions and destruction of the integrated circuits as well as effecting a possible damage to the power supply.
It would be therefore desirable to provide a high voltage isolation circuit for CMOS networks which includes a control device for isolating a high voltage node and a low voltage node.